Domain-Specific Computer Architectures for Emerging Applications Machine Learning and Neural Networks

With the end of Moore?s Law, domain-specific architecture (DSA) has become a crucial mode of implementing future computing architectures. This book discusses the system-level design methodology of DSAs and their applications, providing a unified design process that guarantees functionality, performance, energy efficiency, and real-time responsiveness for the target application.

DSAs often start from domain-specific algorithms or applications, analyzing the characteristics of algorithmic applications, such as computation, memory access, and communication, and proposing the heterogeneous accelerator architecture suitable for that particular application. This book places particular focus on accelerator hardware platforms and distributed systems for various novel applications, such as machine learning, data mining, neural networks, and graph algorithms, and also covers RISC-V open-source instruction sets. It briefly describes the system design methodology based on DSAs and presents the latest research results in academia around domain-specific acceleration architectures.

Providing cutting-edge discussion of big data and artificial intelligence scenarios in contemporary industry and typical DSA applications, this book appeals to industry professionals as well as academicians researching the future of computing in these areas.

Preface. 1 Overview of Domain‑Specific Computing. 2 Machine Learning Algorithms and Hardware Accelerator Customization. 3 Hardware Accelerator Customization for Data Mining Recommendation Algorithms. 4 Customization and Optimization of Distributed Computing Systems for Recommendation Algorithms. 5 Hardware Customization for Clustering Algorithms. 6 Hardware Accelerator Customization Techniques for Graph Algorithms. 7 Overview of Hardware Acceleration Methods for Neural Network Algorithms. 8 Customization of FPGA‑Based Hardware Accelerators for Deep Belief Networks. 9 FPGA‑Based Hardware Accelerator Customization for Recurrent Neural Networks. 10 Hardware Customization/Acceleration Techniques for Impulse Neural Networks. 11 Accelerators for Big Data Genome Sequencing. 12 RISC‑V Open Source Instruction Set and Architecture. 13 Compilation Optimization Methods in the Customization of Reconfigurable Accelerators Index.

Dr. Chao Wang is a Professor with the University of Science and Technology of China, and also the Vice Dean of the School of Software Engineering. He serves as the Associate Editor of ACM TODAES and IEEE/ACM TCBB. Dr. Wang was the recipient of ACM China Rising Star Honorable Mention, and best IP nomination of DATE 2015, Best Paper Candidate of CODES+ISSS 2018. He is a senior member of ACM, senior member of IEEE, and distinguished member of CCF.