Advanced MOS Devices and their Circuit Applications

This text comprehensively discusses the advanced MOS devices and their circuit applications with reliability concerns. Further, an energy-efficient Tunnel FET-based circuit application will be investigated in terms of the output voltage, power efficiency, energy consumption, and performances using the device circuit co-design approach.

The book:

• Discusses advanced MOS devices and their circuit design for energy- efficient systems on chips (SoCs)
• Covers MOS devices, materials, and related semiconductor transistor technologies for the next-generation ultra-low-power applications
• Examines the use of field-effect transistors for biosensing circuit applications and covers reliability design considerations and compact modeling of advanced low-power MOS transistors
• Includes research problem statements with specifications and commercially available industry data in the appendix
• Presents Verilog-A model-based simulations for circuit analysis

The volume provides detailed discussions of DC and analog/RF characteristics, effects of trap-assisted tunneling (TAT) for reliability analysis, spacer-underlap engineering methodology, doping profile analysis, and work-function techniques. It further covers novel MOS devices including FinFET, Graphene field-effect transistor, Tunnel FETS, and Flash memory devices. It will serve as an ideal design book for senior undergraduate students, graduate students, and academic researchers in the fields including electrical engineering, electronics and communication engineering, computer engineering, materials science, nanoscience, and nanotechnology.

Chapter 1

An Overview of DC/RF Performance of Nanosheet Field Effect Transistor for Future Low Power Applications

Arun A V, Sajeesh M, Jobymol Jacob, J Ajayan

Chapter 2

Device Design and Analysis of 3D SCwRD Cylindrical (Cyl) Gate-All-Around (GAA) Tunnel FET using Split-Channel and spacer Engineering

Ankur Beohar, Seema Tiwari, Kavita Khare, Santosh Kumar Vishvakarma

Chapter 3

Investigation of High-K Dielectrics for Single and Multi-Gate FETs

Sresta Valasa, Shubham Tayal, Laxman Raju Thoutam

Chapter 4

Measurement of Back Gate Biasing For Ultra Low Power Subthreshold Logic in FinFET Device

Ajay Kumar Dadoria, Uday Panwar, Narendra Kumar Garg

Chapter 5

Compact Analytical Model for Graphene Field Effect Transistor: Drift-Diffusion Approac

Abhishek Kumar Upadhyay1, Siromani Balmukund Rahi, Billel

Chapter 6

Design of CNTFET-Based Ternary Logic Flip-Flop and Counter Circuits using Unary Operators

Trapti Sharma

Chapter 7

NOVEL RADIATION HARDENED LOW POWER 12 TRANSISTORS SRAM CELL FOR AEROSPACE APPLICATION

Vancha sharath reddy, Arjun singh yadav, Soumya sengupta

Chapter 8

Nanoscale CMOS Static Random Access Memory (SRAM) Design: Trends and Challenges

Sunanda Ambulkar, Jeetendra Kumar Mishra

Chapter 9

Variants based Gate Modification (VGM) technique for reducing leakage power and short channel effect in DSM circuits

Uday Panwar, Ajay Kumar Dadoria

Chapter 10

A Novel Approach for High Speed and low Power by using Nano-VLSI Interconnects

Narendra Kumar Garg , Vivek Singh Kushwah, Ajay Kumar Dadoria

Dr. Ankur Beohar (Senior member IEEE) obtaineda PhD degree in electrical engineering from the Indian Institute of Technology (IIT), Indore, MP, India, in 2018. After getting his PhD, he worked as a postdoctoral fellow in the Device Modeling Group, IISER, Bhopal, and then as a research scientist for one year under awarded Scientist Pool scheme of Council of Scientific and Industrial Research (CSIR), New Delhi. Currently, he is working as an assistant professor at Vellore Institute of Technology (VIT) Bhopal. He is an IEEE Senior Member and a Secretary of IEEE, Circuit and System Society, MP section, India. He completed his M.Tech degree in VLSI and Embedded System Design from MANIT Bhopal and B.Tech (Electronics) from RGPV University Bhopal in 2010 and 2005. He has a research and academic work experience of more than 13 years. He has a renowned research experience in the field of low-power device circuit design Memory Circuit Design and Reliability. His current research is related to new-generation innovative devices, such as optimization of gate all around (GAA)-Tunnel field effect transistor (TFET) with spacer engineering and its circuit applications. Currently, he is working in the research project sanctioned by the Science and Engineering Research Board (SERB) under the Teachers Associateship Research Excellence (TARE) scheme. Dr. Beohar has published more than 35 research publications in various peer- reviewed international conferences and SCI journals. Along with this, he has reviewed more than 100+ journal and conferences articles.

Dr. Abhishek Kumar Upadhyay obtained a PhD in electrical engineering from the Indian Institute of Technology (IIT), Indore, MP, India, in 2019. After getting his PhD, he worked for one year as a postdoctoral fellow in the Model Group, Material to System Integration Laboratory, University of Bordeaux, France, and then as a staff scientist in the Chair of Electronics Devices and Integrated C